A resistive random-access memory (RRAM) is one kind of non-volatile memory. Since the resistive random-access memories have larger storage capability and higher accessing speed, the manufacturers of the memories pay much attention to the development of the resistive random-access memories.
FIG. 1 schematically illustrates the structure of a resistive random-access memory. As shown in FIG. 1, the resistive random-access memory 100 comprises a top electrode 102, an insulation layer 104 and a bottom electrode 106. After the resistive random-access memory is fabricated, the resistive random-access memory is in an initial state.
Before the normal operation of the resistive random-access memory 100, a forming action is performed to apply a first voltage difference (e.g., +3V) to the top electrode 102 and the bottom electrode 106. For example, the top electrode 102 receives a voltage of +3V, and the bottom electrode 106 receives a ground voltage. While the forming action is performed, the cluster of oxygen vacancies in the insulation layer 104 forms a conducting filament 108. In addition, the conducting filament 108 is connected with the top electrode 102 and the bottom electrode 106. After the conducting filament 108 is formed, the forming action is completed. Meanwhile, the region between the top electrode 102 and the bottom electrode 106 has a low resistance value (i.e., in a set state). Consequently, the resistive random-access memory 100 can be normally operated.
Moreover, a reset action may be performed to switch the set state to a reset state (i.e., a high resistance value). While the reset action is performed, a second voltage difference (e.g., −3V) is applied to the top electrode 102 and the bottom electrode 106. For example, the top electrode 102 receives a voltage of −3V, and the bottom electrode 106 receives the ground voltage. After the reset action is completed, the conducting filament 108 within the insulation layer 104 is treated by a redox process. Consequently, the conducting filament 108 is no longer connected between the top electrode 102 and the bottom electrode 106. Meanwhile, the region between the top electrode 102 and the bottom electrode 106 has the high resistance value (i.e., in the reset state).
In case that the resistive random-access memory 100 is in the reset state, the resistive random-access memory 100 may be switched to the set state by a set action. While the set action is performed, a third voltage difference (e.g., +3V) is applied to the top electrode 102 and the bottom electrode 106. For example, the top electrode 102 receives a voltage of +3V, and the bottom electrode 106 receives the ground voltage. After the set action is completed, the region between the top electrode 102 and the bottom electrode 106 has the low resistance value (i.e., in the set state).
Consequently, in response to a program action during a program cycle, the resistive random-access memory 100 can be selectively in the set state through the set action or in the reset state through the rest action. In other words, the set state and the reset state are two storing states of the resistive random-access memory 100.
Moreover, in response to a read action during a read cycle, a read voltage (e.g., 0.1V˜0.5V) is applied to the top electrode 102 and the bottom electrode 106. Consequently, according to the magnitude of a read current generated by the resistive random-access memory 100, the storing state (i.e., the set state or the reset state) of the resistive random-access memory 100 can be realized.
However, since the fabricating process of the resistive random-access memory 100 is usually unstable, the reliability of the resistive random-access memory 100 is not satisfied. Consequently, each set action or each reset action is completed after plural operation periods.
FIG. 2A is a schematic timing waveform diagram of a conventional resistive random-access memory while a set action and a reset action are performed. Generally, the resistive random-access memory is connected with a controlling circuit (not shown). Moreover, the controlling circuit controls the set action or the reset action of the resistive random-access memory.
Generally, each of the set action and the reset action are completed after plural operation periods Oper1˜Oper4. Moreover, each operation period of the set action contains a setting period and a verifying period, and each operation period of the reset action contains a resetting period and a verifying period.
Please refer to the set action of FIG. 2A. During the setting period of the first operation period Oper1, a set voltage Vset (e.g., +3V) is applied to the top electrode and the bottom electrode of the resistive random-access memory. Consequently, the resistive random-access memory is in the set state. During the verifying period of the first operation period Oper1, a read voltage Vv is applied to the top electrode and the bottom electrode of the resistive random-access memory. According to the magnitude of a read current generated by the resistive random-access memory, the control circuit can verify whether the resistive random-access memory is in the set state.
If the control circuit confirms that the resistive random-access memory is in the set state according to the read current, the subsequent procedures of the set action after the first operation period Oper1 will not be performed. Whereas, if the control circuit confirms that the resistive random-access memory is not in the set state according to the read current, the subsequent procedures of the set action corresponding to the operation periods Oper2, Oper3 and/or Oper4 will be performed. That is, plural procedures of the set action corresponding to plural operation periods are possibly performed until the control circuit confirms that the resistive random-access memory is in the set state.
Please refer to the reset action of FIG. 2A. During the resetting period of the first operation period Oper1, a reset voltage Vreset (e.g., −3V) is applied to the top electrode and the bottom electrode of the resistive random-access memory. Consequently, the resistive random-access memory is in the reset state. During the verifying period of the first operation period Oper1, a read voltage Vv is applied to the top electrode and the bottom electrode of the resistive random-access memory. According to the magnitude of a read current generated by the resistive random-access memory, the control circuit can verify whether the resistive random-access memory is in the reset state.
If the control circuit confirms that the resistive random-access memory is in the reset state according to the read current, the subsequent procedures of the set action after the first operation period Oper1 will not be performed. Whereas, if the control circuit confirms that the resistive random-access memory is not in the reset state according to the read current, the subsequent procedures of the set action corresponding to the operation periods Oper2, Oper3 and/or Oper4 will be performed. That is, plural procedures of the reset action are possibly performed until the control circuit confirms that the resistive random-access memory is in the reset state.
FIG. 2B is another schematic timing waveform diagram of a conventional resistive random-access memory while a set action and a reset action are performed. Generally, each of the set action and the reset action are completed after plural operation periods Oper1˜Oper3. Moreover, in each of the set action and the reset action, each operation period contains a setting period, a resetting period and a verifying period. The operation period of the set action contains the setting period, the verifying period and the resetting period sequentially. The operation period of the reset action contains the resetting period, the verifying period and the setting period sequentially.
During the setting period of the first operation period Oper1, a set voltage Vset (e.g., +3V) is applied to the top electrode and the bottom electrode of the resistive random-access memory. Consequently, the resistive random-access memory is in the set state. During the verifying period of the first operation period Oper1, a read voltage Vv is applied to the top electrode and the bottom electrode of the resistive random-access memory. According to the magnitude of a read current generated by the resistive random-access memory, the control circuit can verify whether the resistive random-access memory is in the set state. During the resetting period of the first operation period Oper1, a reset voltage Vreset (e.g., −3V) is applied to the top electrode and the bottom electrode of the resistive random-access memory. Consequently, the resistive random-access memory is in the reset state.
Please refer to the set action of FIG. 2B. During the setting period of the first operation period Oper1, the resistive random-access memory is in the set state. During the verifying period of the first operation period Oper1, the control circuit can verify whether the resistive random-access memory is in the set state according to the magnitude of the read current generated by the resistive random-access memory.
If the control circuit confirms that the resistive random-access memory is in the set state according to the read current, the subsequent procedure of the reset action corresponding to the first operation period Oper1 will not be performed. Meanwhile, the set action is completed. Whereas, if the control circuit confirms that the resistive random-access memory is not in the set state according to the read current, the subsequent procedures of the set action corresponding to the operation periods Oper2 and/or Oper3 will be performed.
As shown in FIG. 2B, the set action is completed after three operation periods Oper1˜Oper3. During the verifying period of the third operation period Oper3, the control circuit verifies that the resistive random-access memory is in the set state. Consequently, the subsequent procedure of the resetting period corresponding to the third operation period Oper3 will not be performed.
Please refer to the reset action of FIG. 2B. During the resetting period of the first operation period Oper1, the resistive random-access memory is in the reset state. During the verifying period of the first operation period Oper1, the control circuit can verify whether the resistive random-access memory is in the reset state according to the magnitude of the read current generated by the resistive random-access memory.
If the control circuit confirms that the resistive random-access memory is in the reset state according to the read current, the subsequent procedure of the set action corresponding to the first operation period Oper1 will not be performed. Meanwhile, the reset action is completed. Whereas, if the control circuit confirms that the resistive random-access memory is not in the reset state according to the read current, the subsequent procedures of the reset action corresponding to the operation periods Oper2 and/or Oper3 will be performed.
As shown in FIG. 2B, the reset action is completed after two operation periods Oper1˜Oper2. During the verifying period of the second operation period Oper2, the control circuit verifies that the resistive random-access memory is in the reset state. Consequently, the subsequent procedure of the set period corresponding to the second operation period Oper2 will not be performed.
However, the above approaches still have some drawbacks. For example, after the set action on the resistive random-access memory is completed, the controlling circuit is still unable to stably control the resistive random-access memory in the set state. In addition, after the reset action on the resistive random-access memory is completed, the controlling circuit is still unable to stably control the resistive random-access memory in the reset state.